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2-mbit (64k x 32) pipelined sram with nobl? architecture cy7c1334h cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05678 rev. *c revised march 20, 2010 features ? pin compatible and functionally equivalent to zbt? devices ? internally self-time d output buffer cont rol to eliminate the need to use oe ? byte write capability ? 64k x 32 common i/o architecture ? 3.3v core power supply ? 3.3v/2.5v i/o operation ? fast clock-to-output times ? 3.5 ns (for 166-mhz device) ? 4.0 ns (for 133-mhz device) ? clock enable (cen ) pin to suspend operation ? synchronous self-timed write ? asynchronous output enable (oe ) ? offered in lead-free jedec-standard 100-pin tqfp package ? burst capability?linear or interleaved burst order ? ?zz? sleep mode option functional description [1] the cy7c1334h is a 3.3v/2.5v, 64k x 32 synchronous-pipelined burst sram designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. the cy7c1334h is equipped with the advanced no bus latency? (nobl?) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. this feature dramatically improves the throughput of the sram, especially in systems that require fre quent write/read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by t he rising edge of the clock. the clock input is qualified by the clock enable (cen ) signal, which, when deasserted, susp ends operation and extends the previous clock cycle. maximum access delay from the clock rise is 3.5 ns (166-mhz device) write operations are controlled by the four byte write select (bw [a:d] ) and a write enable (we ) input. all writes are conducted with on-chip synchronous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tri-state control. in order to avoid bus contention, the output driver s are synchronously tri-stated during the data portion of a write sequence. note: 1. for best-practices recommendations, please refer to the cypress application note system design guidelines on www.cypress.com. a0, a1, a c mode bw a bw b we ce1 ce2 ce3 oe read logic dq s d a t a s t e e r i n g o u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register 1 write address register 2 write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 c adv/ld adv/ld e input register 1 s e n s e a m p s e c lk c en write drivers bw c bw d zz sleep control o u t p u t r e g i s t e r s logic block diagram [+] feedback
cy7c1334h document #: 38-05678 rev. *c page 2 of 13 . selection guide 166 mhz 133 mhz unit maximum access time (t co ) 3.5 4.0 ns maximum operating current (i dd ) 240 225 ma maximum cmos standby current 40 40 ma pin configuration a a a a a 1 a 0 nc/288m nc/144m v ss v dd nc/36m a a a a a nc/4m nc dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a nc nc dq c dq c v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c nc v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d nc a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a adv/ld zz mode nc/72m nc/18m nc/9m cy7c1334h 100-pin tqfp pinout byte b byte a byte c byte d [+] feedback
cy7c1334h document #: 38-05678 rev. *c page 3 of 13 pin definitions name i/o description a0, a1, a input- synchronous address inputs used to select one of the 64k address locations . sampled at the rising edge of the clk. a [1:0] are fed to the two-bit burst counter. bw [a:d] input- synchronous byte write inputs, active low . qualified with we to conduct writes to the sram. sampled on the rising edge of clk. we input- synchronous write enable input, active low . sampled on the rising edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence. adv/ld input- synchronous advance/load input . used to advance the on-chip address counter or load a new address. when high (and cen is asserted low) the internal burs t counter is advanced. when low, a new address can be loaded into the device for an access. after being deselected, adv/ld should be driven low in order to load a new address. clk input-clock clock input . used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only recognized if cen is active low. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/desel ect the device. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/desel ect the device. oe input- asynchronous output enable, asynchronous input, active low . combined with the synchronous logic block inside the device to control the direction of the i/o pins. when low, the i/o pins are allowed to behave as outputs. when deasserted hi gh, i/o pins are tri-stated, and act as input data pins. oe is masked during the data portion of a wr ite sequence, during the first clock when emerging from a deselected state, when the device has been deselected. cen input- synchronous clock enable input, active low . when asserted low the clock signal is recognized by the sram. when deasserted high the clock si gnal is masked. since deasserting cen does not deselect the device, cen can be used to extend the previous cycle when required. zz input- asynchronous zz ?sleep? input . this active high input places the de vice in a non-time critical ?sleep? condition with data integrity preserved. during normal operation, this pin can be connected to v ss or left floating. dqs i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-c hip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by a [16:0] during the clock rise of the read cycle. the direction of the pins is controlled by oe and the internal control logic. when oe is asserted low, the pins can behave as outputs. when high, dq s are placed in a tri-state condition. th e outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of oe . mode input strap pin mode input. selects the burst order of the device. when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects inter- leaved burst sequence. v dd power supply power supply inputs to the core of the device . v ddq i/o power supply power supply for the i/o circuitry . v ss ground ground for the device . v ssq i/o ground ground for the i/o circuitry . should be connected to the ground of the system nc no connects . not internally connected to the die. 4m, 9m,18m, 72m, 14 4m, 288m, 576m and 1g are address expansion pins and are not internally connected to the die. [+] feedback
cy7c1334h document #: 38-05678 rev. *c page 4 of 13 functional overview the cy7c1334h is a synchronous-pipelined burst sram designed specifically to el iminate wait states during write/read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock signal is qualified with the clock enable input signal (cen ). if cen is high, the clock signal is not recognized and all internal states are maintained. all synchronous operations are qualified with cen . all data outputs pass through output registers controlled by the rising edge of the clock. maximum access delay from the clock rise (t co ) is 3.5 ns (166-mhz device). accesses can be initiated by asserting all three chip enables (ce 1 , ce 2 , ce 3 ) active at the rising edge of the clock. if clock enable (cen ) is active low and adv/ld is asserted low, the address presented to the device will be latched. the access can either be a read or write operation, depending on the status of the write enable (we ). bw [a:d] can be used to conduct byte write operations. write operations are qualified by the write enable (we ). all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) simplify depth expansion. all operations (reads, writes, and deselects) are pipelined. adv/ld should be driven low once the device has been deselected in order to load a new address for the next operation. single read accesses a read access is initiated when the following conditions are satisfied at clo ck rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, (3) the write enable input signal we is deasserted high, and (4) adv/ld is asserted low. the address presented to the address inputs is latched into the address register and presented to the memory core and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the input of the ou tput register. at the rising edge of the next clock the requested data is allowed to propagate through the output register a nd onto the data bus, provided oe is active low. after the first clock of the read access the output buffers are controlled by oe and the internal control logic. oe must be driven low in order fo r the device to drive out the requested data. during the second clock, a subsequent operation (read/write/deselect) can be initiated. deselecting the device is also pipelined. therefore, when the sram is deselected at clock rise by one of the chip enable signals, its output will tri-state following the next clock rise. burst read accesses the cy7c1334h has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four reads without reassertin g the address inputs. adv/ld must be driven low in order to load a new address into the sram, as described in the single read access section above. the sequence of the burst counte r is determined by the mode input signal. a low input on mode selects a linear burst mode, a high selects an interleaved burst sequence. both burst counters use a0 and a1 in the burst sequence, and will wrap around when incremented su fficiently. a high input on adv/ld will increment the internal burst counter regardless of the state of chip enables inputs or we . we is latched at the beginning of a burst cycle. ther efore, the type of access (read or write) is maintained throughout the burst sequence. single write accesses write accesses are initiated when the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, and (3) the write signal we is asserted low. the address presented to the address inputs is loaded into the address register. the write signals are latched into the control logic block. on the subsequent clock rise the data lines are automatically tri-stated regardless of the state of the oe input signal. this allows the external logic to present the data on dqs and dqp [a:d] . in addition, the address for the subsequent access (read/write/deselect) is latched into the address register (provided the appropriate control signals are asserted). on the next clock rise the data presented to dqs (or a subset for byte write operations, see write cycle description table for details) inputs is latched into the device and the write is complete. the data written during the wr ite operation is controlled by bw [a:d] signals. the cy7c1334h provides byte write capability that is described in the write cycle description table. asserting the write enable input (we ) with the selected byte write select (bw [a:d] ) input will selectively write to only the desired bytes. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. byte write capability has been included in order to greatly simplify read/modify/w rite sequences, which can be reduced to simple byte write operations. because the cy7c1334h is a common i/o device, data should not be driven into the device while the outputs are active. the output enable (oe ) can be deasserted high before presenting data to the dqs. doing so will tri-state the output drivers. as a safety precaution, dqs are automatically tri-stated during the data porti on of a write cycle, regardless of the state of oe . burst write accesses the cy7c1334h has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four write operations without reasserting the address inputs. adv/ld must be driven low in order to load the initial address, as described in th e single write access section above. when adv/ld is driven high on the subsequent clock rise, the chip enables (ce 1 , ce 2 , and ce 3 ) and we inputs are ignored and the burst counter is incremented. the correct bw [a:d] inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , and ce 3 , must remain inactive for the duration of t zzrec after the zz input returns low. [+] feedback
cy7c1334h document #: 38-05678 rev. *c page 5 of 13 interleaved burst address table (mode = floating or v dd ) first address a1, a0 second address a1, a0 third address a1, a0 fourth address a1, a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1, a0 second address a1, a0 third address a1, a0 fourth address a1, a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 cycle description truth table [2, 3, 4, 5, 6, 7, 8] operation address used ce zz adv/ld we bw x oe cen clk dq deselect cycle none h l l x x x l l-h tri-state continue deselect cycle none x l h x x x l l-h tri-state read cycle (begin burst) exte rnal l l l h x l l l-h data out (q) read cycle (continue burst) next x l h x x l l l-h data out (q) nop/dummy read (begin burst) external l l l h x h l l-h tri-state dummy read (continue burst) next x l h x x h l l-h tri-state write cycle (begin burst) external l l l l l x l l-h data in (d) write cycle (continue burst) next x l h x l x l l-h data in (d) nop/write abort (begin burst) none l l l l h x l l-h tri-state write abort (continue burst) next x l h x h x l l-h tri-state ignore clock edge (stall) current x l x x x x h l-h - sleep mode none x h x x x x x x tri-state notes: 2. x = ?don't care.? h = high, l = low. ce stands for all chip enables active. bwx = 0 signifies at least one byte write select is active, bwx = valid signifies that the desired byte write selects are asserted, see write cycle description table for details. 3. write is defined by bw [a:d] , and we . see write cycle descriptions table. 4. when a write cycle is detected, all i/os are three-stated, even during byte writes. 5. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 6. cen = h, inserts wait states. 7. device will power-up deselected and the i/os in a three-state condition, regardless of oe . 8. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle dqs a nd dqp [a:d] = tri-state when oe is inactive or when the device is deselected, and dqs = data when oe is active. [+] feedback
cy7c1334h document #: 38-05678 rev. *c page 6 of 13 write cycle description [2, 3] function we bw d bw c bw b bw a read h x x x x write ? no bytes written l h h h h write byte a ? (dq a ) lhhhl write byte b ? (dq b )lhhlh write bytes a, b l h h l l write byte c ? (dq c )lhlhh write bytes c,a l h l h l write bytes c, b l h l l h write bytes c, b, a l h l l l write byte d ? (dq d )llhhh write bytes d, a l l h h l write bytes d, b l l h l h write bytes d, b, a l l h l l write bytes d, c l l l h h write bytes d, c, a l l l h l write bytes d, c, b l l l l h write all bytes l l l l l zz mode electrical characteristics parameter description test conditions min. max. unit i ddzz sleep mode standby current zz > v dd ? 0.2v 40 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz active to sleep current t his parameter is sampled 2t cyc ns t rzzi zz inactive to exit sleep current this parameter is sampled 0 ns [+] feedback
cy7c1334h document #: 38-05678 rev. *c page 7 of 13 maximum rating (above which the useful life may be impaired. for user guide- lines not tested.) storage temperature ..................................... ? 65c to +150c ambient temperature with power applied .................................................. ? 55c to +125c supply voltage on v dd relative to gnd .........? 0.5v to +4.6v supply voltage on v ddq relative to gnd .......? 0.5v to +v dd dc voltage applied to outputs in tri-state ................................................? 0.5v to v ddq + 0.5v dc input voltage ....................................... ? 0.5v to v dd + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current.......... .............. .............. .............. > 200 ma operating range range ambient temperature (t a ) v dd v ddq com?l 0c to +70c 3.3v - 5%/+10% 2.5v - 5% to v dd ind?l ?40c to +85c electrical characteristics over the operating range [9, 10] parameter description test conditions min. max. unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage for 3.3v i/o 3.135 v dd v for 2.5v i/o 2.375 2.625 v v oh output high voltage for 3.3v i/o, i oh = ?4.0 ma 2.4 v for 2.5v i/o, i oh = ?1.0 ma 2.0 v ol output low voltage for 3.3v i/o, i ol = 8.0 ma 0.4 v for 2.5v i/o, i ol = 1.0 ma 0.4 v ih input high voltage [9] for 3.3v i/o 2.0 v dd + 0.3v v for 2.5v i/o 1.7 v dd + 0.3v v il input low voltage [9] for 3.3v i/o ?0.3 0.8 v for 2.5v i/o ?0.3 0.7 i x input leakage current except zz and mode gnd v i v ddq ?5 5 a input current of mode input = v ss ? 30 a input = v dd 5 a input current of zz input = v ss ? 5 a input = v dd 30 a i oz output leakage current gnd v i v ddq, output disabled ? 5 5 a i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 6-ns cycle, 166 mhz 240 ma 7.5-ns cycle, 133 mhz 225 ma i sb1 automatic ce power-down current?ttl inputs v dd = max, device deselected, v in v ih or v in v il f = f max = 1/t cyc 6-ns cycle, 166 mhz 100 ma 7.5-ns cycle, 133 mhz 90 ma i sb2 automatic ce power-down current?cmos inputs v dd = max, device deselected, v in 0.3v or v in > v ddq ? 0.3v, f = 0 all speeds 40 ma i sb3 automatic ce power-down current?cmos inputs v dd = max, device deselected, or v in 0.3v or v in > v ddq ? 0.3v f = f max = 1/t cyc 6-ns cycle, 166 mhz 85 ma 7.5-ns cycle, 133 mhz 75 ma i sb4 automatic ce power-down current?ttl inputs v dd = max, device deselected, v in v ih or v in v il , f = 0 all speeds 45 ma notes: 9. overshoot: v ih (ac) < v dd +1.5v (pulse width less than t cyc /2), undershoot: v il (ac)> ?2v (pulse width less than t cyc /2). 10. t power-up : assumes a linear ramp from 0v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd . [+] feedback
cy7c1334h document #: 38-05678 rev. *c page 8 of 13 capacitance [11] parameter description test conditions 100 tqfp max. unit c in input capacitance t a = 25c, f = 1 mhz, v dd = 3.3v, v ddq = 2.5v 5pf c clk clock input capacitance 5 pf c i/o input/output capacitance 5 pf thermal resistance [11] parameter description test conditions 100 tqfp package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51 30.32 c/w jc thermal resistance (junction to case) 6.85 c/w ac test loads and waveforms notes: 11. tested initially and after any design or proce ss changes that may affect these parameters. output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 1.5v 3.3v all input pulses v ddq gnd 90% 10% 90% 10% 1 ns 1 ns (c) 3.3v i/o test load output r = 1667 ? r =1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% 1 ns 1 ns (c) 2.5v i/o test load [+] feedback
cy7c1334h document #: 38-05678 rev. *c page 9 of 13 switching characteristics over the operating range [12, 13] 166 mhz 133 mhz parameter description min. max. min. max. unit t power v dd (typical) to the first access [14] 11ms clock t cyc clock cycle time 6.0 7.5 ns t ch clock high 2.5 3.0 ns t cl clock low 2.5 3.0 ns output times t co data output valid after clk rise 3.5 4.0 ns t doh data output hold after clk rise 1.5 1.5 ns t clz clock to low-z [15, 16, 17] 00ns t chz clock to high-z [15, 16, 17] 3.5 4.0 ns t oev oe low to output valid 3.5 4.0 ns t oelz oe low to output low-z [15, 16, 17] 00ns t oehz oe high to output high-z [15, 16, 17] 3.5 4.0 ns set-up times t as address set-up before clk rise 1.5 1.5 ns t als adv/ld set-up before clk rise 1.5 1.5 ns t wes gw , bw [a:d] set-up before clk rise 1.5 1.5 ns t cens cen set-up before clk rise 1.5 1.5 ns t ds data input set-up before clk rise 1.5 1.5 ns t ces chip enable set-up before clk rise 1.5 1.5 ns hold times t ah address hold after clk rise 0.5 0.5 ns t alh adv/ld hold after clk rise 0.5 0.5 ns t weh gw , bw [a:d] hold after clk rise 0.5 0.5 ns t cenh cen hold after clk rise 0.5 0.5 ns t dh data input hold after clk rise 0.5 0.5 ns t ceh chip enable hold after clk rise 0.5 0.5 ns notes: 12. test conditions shown in (a), (b) and (c) of ac test loads. 13. timing reference level is 1.5v when v ddq = 3.3v and 1.25v when v ddq = 2.5v. 14. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd minimum initially before a read or write operation can be initiated. 15. t chz , t clz , t oelz , and t oehz are specified with ac test conditions s hown in part (b) of ac test loads. transition is measured 200 mv from steady-state vo ltage. 16. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but refl ect parameters guaranteed over worst case user conditions. device is designed to achieve tri-state prior to low-z under the same system conditions 17. this parameter is sampled and not 100% tested. [+] feedback
cy7c1334h document #: 38-05678 rev. *c page 10 of 13 switching waveforms read/write timing [18, 19, 20] notes: 18. for this waveform zz is tied low. 19. when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high. 20. order of the burst sequence is determined by the status of the mode (0 = linear, 1 = interleaved). burst operations are opti onal. write d(a1) 123 456789 clk t cyc t cl t ch 10 ce t ceh t ces we cen t cenh t cens bw [a:d] adv/ld t ah t as address a1 a2 a3 a4 a5 a6 a7 t dh t ds data i n-out (dq) t clz d(a1) d(a2) d(a5) q(a4) q(a3) d(a2+1) t doh t chz t co write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect oe t oev t oelz t oehz t doh don?t care undefined q(a6) q(a4+1) [+] feedback
cy7c1334h document #: 38-05678 rev. *c page 11 of 13 nop, stall, and deselect cycles [18, 19, 21] zz mode timing [22, 23] notes: 21. the ignore clock edge or stall cycle (clock 3) illustrated cen being used to create a pause. a write is not performed during this cycle. 22. device must be deselected when entering zz mode. see cycle description table for a ll possible signal conditions to deselect the device. 23. i/os are in high-z when exiting zz sleep mode. switching waveforms (continued) read q(a3) 456 78910 clk ce we cen bw [a:d] adv/ld address a3 a4 a5 d(a4) data in-out (dq) a1 q(a5) write d(a4) stall write d(a1) 123 read q(a2) stall nop read q(a5) deselect continue deselect don?t care undefined t chz a2 d(a1) q(a2) q(a3) t zz i supply clk zz t zzrec a ll inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only [+] feedback
cy7c1334h document #: 38-05678 rev. *c page 12 of 13 ? cypress semiconductor corporation, 2006-2010. the information contained herein is subject to change without notice. cypress semiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under pate nt or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical cont rol or safety applications, unless pursuant to an express writt en agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. nobl and no bus latency are trademarks of cypress semiconduc tor corporation. zbt is a trademark of integrated device technology, inc. all product and company names mentioned in this document are the trademarks of their respective holders. ordering information cypress offers other versions of this type of product in many different configuratio ns and features. the following table contai ns only the list of parts t hat are currently available. for a complete listing of all options, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. cypress maintains a worldwide network of offices, solution cent ers, manufacturer's representativ es and distributors. to find th e office closest to you, visit us at http://www.cypress.com/go/datasheet/offices . speed (mhz) ordering code package diagram package type operating range 166 CY7C1334H-166AXC 51-85050 100-pin thin quad fl at pack (14 x 20 x 1.4 mm) lead-free commercial package diagram 100-pin tqfp (14 x 20 x 1.4 mm) (51-85050) 51-85050-*c [+] feedback
cy7c1334h document #: 38-05678 rev. *c page 13 of 13 document history page document title: cy7c1334h 2-mbit (64k x 32 ) pipelined sram with nobl? architecture document number: 38-05678 rev. ecn no. issue date orig. of change description of change ** 347357 see ecn pci new data sheet *a 424820 see ecn rxu changed address of cypress semiconductor corporation on page# 1 from ?3901 north first street? to ?198 champion court? changed three-state to tri-state. modified ?input load? to ?input leakage current except zz and mode? in the electrical characteristics table. modified test condition from v ddq < v dd to v ddq < v dd replaced package name column with package diagram in the ordering information table. replaced package diagram of 51-85050 from *a to *b *b 459347 see ecn nxr converted from preliminary to final included 2.5v i/o option updated the ordering information table. *c 2896585 03/20/2010 njy removed obsolete part numbers from ordering information table and updated package diagrams. [+] feedback

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